Vicuna - a flexible and scalable RISC-V vector coprocessor

Vicuna is an open-source 32-bit integer vector coprocessor written in SystemVerilog that implements version 1.0 of the RISC-V “V” Vector extension specification. More precisely, Vicuna complies with the Zve32x extension, a variant of the V extension aimed at embedded processors that do not require 64-bit elements or floating-point support (see Sect. 18.2 of the specification for details). As such, Vicuna supports vector element widths of 8, 16, and 32 bits and implements all vector load and store, vector integer 1, vector fixed-point, vector integer reduction, vector mask, and vector permutation instructions.

Vicuna is a coprocessor and thus requires a main processor to function. It uses the OpenHW Group’s CORE-V eXtension Interface (CORE-V-XIF) as interface to the main core. Currently, the CV32E40X core or a modified version of the Ibex core serves as the main core.

Vicuna is extensively configurable. For instance, the width of the vector registers, the number and layout of its execution pipelines and the width of its memory interface are configurable. The following figure gives a high-level overview of Vicuna.

_images/vproc_overview.svg

Each of Vicuna’s vector pipelines can host one or multiple vector execution units. Vicuna currently offers the following units:

  • VLSU: The vector load and store unit, responsible for loading and storing memory data to and from vector registers.

  • VALU: The vector arithmetic and logic unit executes most vector arithmetic and vector mask instructions.

  • VMUL: The vector multiplier implements the vector multiplication instructions.

  • VSLD: The vector slide unit takes care of the vector slide instructions.

  • VELEM: The vector element unit uses element-wise processing to implement several vector permutation, many vector mask, and the vector reduction instructions. It is also the only unit capable of writing back data to the general-purpose registers in the main core.

Getting Started

Clone Vicuna’s repository, as well as the repository’s submodules, with the following commands:

git clone https://github.com/vproc/vicuna.git
cd vicuna
git submodule update --init --recursive

Then, follow the instructions in the user guide to get started with using Vicuna.

Footnotes

1

Currently, the vector integer divide instructions (i.e., vdiv, vdivu, vrem, and vremu) are still missing.